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德州仪器的以太网收发器IC TLK6002ZEU
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TI 主页 > 半导体 > 接口 > 串行器、解串器 > 电信和无线串行器/解串器 > TLK6002
德州仪器的 2 通道 0.47Gbps 至 6.25Gbps 多速率收发器芯片
Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver
TLK6002的说明
The TLK6002 is a member of a portfolio of multi-gigabit transceivers, intended for use in ultra-high-speed bi-directional point-to-point data transmission systems. It is specifically intended for base station RRH (Remote Radio Head) application, but may also be used in other high speed applications. The TLK6002 supports a serial interface speed of 0.470 Gbps to 6.25 Gbps. Rate support includes all the CPRI and OBSAI rates (0.6144/0.768/1.2288/1.536/2.4576/3.072/4.9152/6.144 Gbps) using a single fixed reference clock frequency (either 122.88 MHz or 153.6 MHz).
TLK6002 20-bit parallel interface operates in 1.5V or 1.8V HSTL single-ended format. The 20-bit interface allows low speed signals on the parallel side and therefore enabling the use of low cost FPGA in the system design. The parallel interface can be programmed to be in SDR (Single Data Rate) or DDR (Double Data Rate) modes. The line rate may be set to full (≤6.25Gbps), half (≤3.75Gbps), quarter (≤1.88Gbps) or eighth (≤0.94Gbps). The line rate can be set using either device inputs or software control registers.
The TLK6002 performs data conversion parallel-to-serial, serial-to-parallel and clock extraction as a physical layer interface device. The serial transceiver interface operates at a maximum serial data rate of 6.25 Gbps.
TLK6002 accepts single-ended HSTL signals at its parallel transmit and receive data buses. If the internal 8B/10B coding and decoding are enabled, TDA/B_[19:0] are latched by TXCLK_A/B and sent to the internal 8b/10b encoder, where the resulting encoded words are serialized and transmitted differentially using a line clock derived from the SERDES reference clock at the desired line rate. If the internal coding and decoding are disabled, TDA/B_[19:0] are defined as 20-bits of data being serialized and transmitted unmodified according to the desired line rate.
The receive direction performs the serial-to-parallel conversion on the input serial data synchronizing the resulting 20-bit parallel data to the recovered byte clock (RXCLK_A/B). The optionally decoded receive data is available on the RDA/B_[19:0] output signals.
The serial transmitter and receiver are implemented using differential Current Mode Logic (CML) with integrated termination resistors.
The TLK6002 provides two local (parallel side) and two remote (serial side) loopback modes for self-test and system diagnostic purposes.
The TLK6002 has an integrated loss of signal (LOS) detection function, which is asserted in conditions where the serial input signal does not have sufficient voltage amplitude (≤75 mVdfpp). Note that the input signal must be ≥150 mVdfpp when loss of signal replacement of the receive datapath data is enabled (register bit 6.6).
TLK6002的特性
Dual Channel 470Mbps to 6.25Gbps Continuous/Multi-Rate Transceiver
Supports all CPRI and OBSAI Data Rates
Integrated Latency Measurement Function, Accuracy of ±814 ps
CPRI/OBSAI Automated Rate Sense (ARS) Function
Supports SERDES Operation, 8B/10B Data Modes (20-bit and 16-bit + Controls)
20-bit HSTL Single-Ended Parallel Data Interface (Integrated Source and
End Termination)
Shared or Independent Reference Clock per Channel
Latency/Depth Configurable Transmit and Receive FIFOs.
Loopback Capability (Serial and Parallel Side), OBSAI Compliant
Supports Serial Retime Operation
Supports PRBS (27–1), (223 – 1) and (231–1) and
CRPAT Long/Short Generation and Verification
Dual Power Supply: 1.0V Core, and 1.5V/1.8V I/O Nominal Supply
Serial Side Three Tap Transmit De-emphasis and Receive Adaptive Equalization
to Allow Extended Backplane Reach
Programmable Output Swing on Serial Output
Minimum Receiver Differential Input Thresholds of 100mVdfpp
Loss of Signal (LOS) detection (≤75 mVdfpp)
Interface to Back Plane, Copper Cables, or Optical Modules
Hot Plug Protection
JTAG; IEEE 1149.1 /1149.6 Test Interface
MDIO; IEEE 802.3 Clause-22 Support
65nm Advanced CMOS Technology
Industrial Ambient Operating Temp(–40°C to 85°C) at Full Rate
Device Package; 324 PBGA
TLK6002的应用 APPLICATIONS
WI Infrastructure
CPRI and OBSAI Links
Proprietary Links
Backplane
High Speed Point- to-Point Transmission Systems
WI基建
CPRI和OBSAI链接的
专有链接
背板
高速点对点点对点传输系统
深圳市鹏展翅电子有限公司(pzcdz),主营TI(德州仪器,包括TI/BB/NS等品牌)、ADI(亚德诺)品牌全新原装集成电路（IC），公司团队专注于TI品牌原装进口集成电路10多年,现货多多，TI/BB系列很多型号具有价格优势，可全线订货。欢迎各新老客户咨询选购。鹏展翅网站 http://pzcdz.ic.net.cn 电话: 0755-32918091/13713594500 du755@qq.com QQ:447309662 微信: dujunjie0755
TI 主页 > 半导体 > 接口 > 串行器、解串器 > 电信和无线串行器/解串器 > TLK6002
德州仪器的 2 通道 0.47Gbps 至 6.25Gbps 多速率收发器芯片
Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver
TLK6002的说明
The TLK6002 is a member of a portfolio of multi-gigabit transceivers, intended for use in ultra-high-speed bi-directional point-to-point data transmission systems. It is specifically intended for base station RRH (Remote Radio Head) application, but may also be used in other high speed applications. The TLK6002 supports a serial interface speed of 0.470 Gbps to 6.25 Gbps. Rate support includes all the CPRI and OBSAI rates (0.6144/0.768/1.2288/1.536/2.4576/3.072/4.9152/6.144 Gbps) using a single fixed reference clock frequency (either 122.88 MHz or 153.6 MHz).
TLK6002 20-bit parallel interface operates in 1.5V or 1.8V HSTL single-ended format. The 20-bit interface allows low speed signals on the parallel side and therefore enabling the use of low cost FPGA in the system design. The parallel interface can be programmed to be in SDR (Single Data Rate) or DDR (Double Data Rate) modes. The line rate may be set to full (≤6.25Gbps), half (≤3.75Gbps), quarter (≤1.88Gbps) or eighth (≤0.94Gbps). The line rate can be set using either device inputs or software control registers.
The TLK6002 performs data conversion parallel-to-serial, serial-to-parallel and clock extraction as a physical layer interface device. The serial transceiver interface operates at a maximum serial data rate of 6.25 Gbps.
TLK6002 accepts single-ended HSTL signals at its parallel transmit and receive data buses. If the internal 8B/10B coding and decoding are enabled, TDA/B_[19:0] are latched by TXCLK_A/B and sent to the internal 8b/10b encoder, where the resulting encoded words are serialized and transmitted differentially using a line clock derived from the SERDES reference clock at the desired line rate. If the internal coding and decoding are disabled, TDA/B_[19:0] are defined as 20-bits of data being serialized and transmitted unmodified according to the desired line rate.
The receive direction performs the serial-to-parallel conversion on the input serial data synchronizing the resulting 20-bit parallel data to the recovered byte clock (RXCLK_A/B). The optionally decoded receive data is available on the RDA/B_[19:0] output signals.
The serial transmitter and receiver are implemented using differential Current Mode Logic (CML) with integrated termination resistors.
The TLK6002 provides two local (parallel side) and two remote (serial side) loopback modes for self-test and system diagnostic purposes.
The TLK6002 has an integrated loss of signal (LOS) detection function, which is asserted in conditions where the serial input signal does not have sufficient voltage amplitude (≤75 mVdfpp). Note that the input signal must be ≥150 mVdfpp when loss of signal replacement of the receive datapath data is enabled (register bit 6.6).
TLK6002的特性
Dual Channel 470Mbps to 6.25Gbps Continuous/Multi-Rate Transceiver
Supports all CPRI and OBSAI Data Rates
Integrated Latency Measurement Function, Accuracy of ±814 ps
CPRI/OBSAI Automated Rate Sense (ARS) Function
Supports SERDES Operation, 8B/10B Data Modes (20-bit and 16-bit + Controls)
20-bit HSTL Single-Ended Parallel Data Interface (Integrated Source and
End Termination)
Shared or Independent Reference Clock per Channel
Latency/Depth Configurable Transmit and Receive FIFOs.
Loopback Capability (Serial and Parallel Side), OBSAI Compliant
Supports Serial Retime Operation
Supports PRBS (27–1), (223 – 1) and (231–1) and
CRPAT Long/Short Generation and Verification
Dual Power Supply: 1.0V Core, and 1.5V/1.8V I/O Nominal Supply
Serial Side Three Tap Transmit De-emphasis and Receive Adaptive Equalization
to Allow Extended Backplane Reach
Programmable Output Swing on Serial Output
Minimum Receiver Differential Input Thresholds of 100mVdfpp
Loss of Signal (LOS) detection (≤75 mVdfpp)
Interface to Back Plane, Copper Cables, or Optical Modules
Hot Plug Protection
JTAG; IEEE 1149.1 /1149.6 Test Interface
MDIO; IEEE 802.3 Clause-22 Support
65nm Advanced CMOS Technology
Industrial Ambient Operating Temp(–40°C to 85°C) at Full Rate
Device Package; 324 PBGA
TLK6002的应用 APPLICATIONS
WI Infrastructure
CPRI and OBSAI Links
Proprietary Links
Backplane
High Speed Point- to-Point Transmission Systems
WI基建
CPRI和OBSAI链接的
专有链接
背板
高速点对点点对点传输系统
深圳市鹏展翅电子有限公司(pzcdz),主营TI(德州仪器,包括TI/BB/NS等品牌)、ADI(亚德诺)品牌全新原装集成电路（IC），公司团队专注于TI品牌原装进口集成电路10多年,现货多多，TI/BB系列很多型号具有价格优势，可全线订货。欢迎各新老客户咨询选购。鹏展翅网站 http://pzcdz.ic.net.cn 电话: 0755-32918091/13713594500 du755@qq.com QQ:447309662 微信: dujunjie0755
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